Logic simulators have been used for many years by designers to test the integrity of their logic designs without requiring building and testing of the actual logic design. The logic simulator simulates the functions performed by the specific design and provides the design engineer with an opportunity to examine the signals generated by the design. From an analysis of the simulated signals, the designer may uncover design flaws.
When a design error is identified, the logic simulator permits the designer to easily modify the design and rerun the logic simulation. The ability to change a design and quickly test the changed design has significantly reduced the overall circuit design time. As a result of these advantages of simulators, designers have come to rely on simulators to uncover errors in their designs and to quickly test the new design for errors.
The above described design approach using simulators is most suitable for relatively simple logic simulations. When one attempts to simulate very complex logic networks, however, the simulator running time may last for many hours and in the more complex logic networks, the simulation may take many days to complete. This is due primarily to the greater number of circuits being simulated. During such simulations, some of the simulation data is dumped to an output trace file. In the event an error is found in the logic design being simulated, typical simulators must rely on the data in the trace file. Since the amount of data available in typical trace files is limited, multiple simulations may be needed in order to completely test a logic design.
In searching for a solution to the above mentioned problems, a checkpoint scheme has been developed which allows the designer to rerun a simulation at a desired checkpoint thereby making it easier to observe simulated signals at different times. This technique involves periodically storing the data signal values for the logic network and discarding some of the data signals created at simulation cycles other than those that are saved. Checkpointing allows the designer to rerun a simulation starting at many but not all previously simulated machine cycles. If the exact machine cycle is not checkpointed and, is not available, then the simulator selects the nearest earlier checkpoint and reruns the simulation starting there. The simulation will arrive at the desired machine cycle after a short delay. However, this approach, like others that have been tried, requires a very large number storage locations in order to provide checkpointing. Hence, the length of simulations that can be effectively evaluated and rerun using checkpoint data is limited by the amount of checkpoint memory available to the simulator.
The problem of availability of memory for storing data signals becomes much more acute when the network being simulated includes one or more memories. In existing simulators, each memory location in the network written to during the course of a simulation requires a comparable amount of memory for storing simulated data. As the size and number of the memories increase, the size of the logic network connected thereto becomes larger and as the simulation time becomes longer, the memory requirements of the simulator become increasingly larger and ultimately memory size limitations of the simulator prevent the simulator from performing uninterrupted simulations of a desired length.